Many of today's I/O driver specifications require very small output slew rate variation; particularly specifications for multi-I/O busses. Through network analysis, an optimal output edge rate can be determined to minimize Inter Symbol Interference (ISI) and signal propagation time, and thereby increase the maximum operating frequency of the system. Deviating from this optimal edge rate typically has unfavorable timing and signal integrity implications.
As is known among I/O and System designers, driver output slew rate variation is primarily a function of the driver circuit topology, varying operating conditions, such as voltage and temperature, silicon process variation and the particular application load network. As higher operating frequencies and stricter timing requirements have forced tighter output slew variation specifications, it has become necessary to actively compensate the driver to comply with these specifications and system requirements. Moreover, this class of timing and signal integrity problems will become even more pronounced in the future as both buss operating frequencies and silicon device parametric variations are expected to increase.
Current state of the art techniques to control slew rate variation utilize a concept known as “Process/voltage/temperature (PVT) Correlation.” The design engineer analyzes a circuit to determine the sensitivities and effect of PVT variation on a parameter of interest. In this situation, the parameter of interest is driver output slew rate. Once sensitivities have been determined, a reference circuit is designed such that an easily measurable variable, e.g., impedance, is affected by PVT variation in a manner that correlates reasonably well to the driver output slew rate. For example, assuming analysis shows the process variation of nFET transconductance has the largest, albeit not the only, effect on output slew rate, a sensing circuit would be designed to compare the transconductance of sample nFETs to an ideal reference in order to compensate the driver. However, first order parametric correlation is far from perfect and second relationships are completely ignored. Further, as the reference circuit is much less complex than the compensated circuit and measures a DC variable parameter to compensate a quasi-related AC variable parameter, the compensation is not optimum.
Operation of the suboptimum system works as follows. If the relative strength of the pull down is weak, the comparison of the voltage divider to the reference signal will present a logic ‘1’ to the controller which will in turn enable additional PVTx bits, adding nFET “fingers” and increasing the effective strength of the pull down. Conversely, if the relative strength of the pull down is strong, the comparison of the voltage divider to the reference signal will present a logic ‘0’ to the controller which will in turn disable additional PVTx bits, subtracting NFET “fingers” and decreasing the effective strength of the pull down. This process iterates until the voltage divider signal is equal to the reference voltage.
As discussed above, today's specifications require tight slew rate variation such that a reference circuit must be designed with DC sensitivity to PVT variation that closely mimics that of driver slew rate variation. Using these correlative techniques renders this task virtually impossible with the required degree of accuracy. Other deficiencies in this technique arise in that only one or two reference circuits are used to determine the PVT bit settings for potentially hundreds of drivers across the chip completely ignoring output slew variation caused by across chip, load and local power supply variation.